27 lines
394 B
Verilog
27 lines
394 B
Verilog
`timescale 1ns / 1ps
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module tb;
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reg [3:0] char;
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wire [6:0] LED;
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integer i;
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LEDdecoder dut (
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.char(char),
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.LED (LED)
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);
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initial begin
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$dumpfile("wave.vcd");
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$dumpvars(0, tb);
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for (i = 0; i < 16; i = i + 1) begin
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char = i;
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#10;
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$display("char=%h LED{a..g}=%b", char, LED);
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end
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$finish;
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end
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endmodule
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