61 lines
1.1 KiB
Verilog
61 lines
1.1 KiB
Verilog
`timescale 1ns / 1ps
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module tb_driver;
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reg clk = 0;
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reg reset = 1;
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wire an3, an2, an1, an0;
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wire a, b, c, d, e, f, g, dp;
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FourDigitLEDdriver dut (
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.clk(clk),
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.reset(reset),
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.an3(an3),
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.an2(an2),
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.an1(an1),
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.an0(an0),
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.a(a),
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.b(b),
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.c(c),
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.d(d),
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.e(e),
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.f(f),
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.g(g),
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.dp(dp)
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);
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always #5 clk = ~clk; // 100 MHz
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wire [3:0] low = ~{an3, an2, an1, an0};
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always @(low)
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if ((low & (low - 1)) != 0)
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$display("ERROR t=%0t: επικάλυψη ανόδων, an=%b", $time, {an3, an2, an1, an0});
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always @(an3 or an2 or an1 or an0)
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$display(
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"t=%0t state=%b digit=%h an=%b%b%b%b seg(abcdefg)=%b%b%b%b%b%b%b",
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$time,
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dut.state,
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dut.digit,
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an3,
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an2,
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an1,
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an0,
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a,
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b,
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c,
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d,
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e,
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f,
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g
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);
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initial begin
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$dumpfile("wave_driver.vcd");
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$dumpvars(0, tb_driver);
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#100 reset = 0;
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#20000 $finish;
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end
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endmodule
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