Initial commit
This commit is contained in:
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## This file is a general .xdc for the Spartan-7 Boolean Board
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### Clock Signal
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set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { clk }];
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create_clock -add -name sys_clk -period 10.00 -waveform {0 5} [get_ports { clk }];
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### 7-Segment Display
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set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { a }];
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set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { b }];
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set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { c }];
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set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { d }];
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set_property -dict { PACKAGE_PIN A7 IOSTANDARD LVCMOS33 } [get_ports { e }];
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set_property -dict { PACKAGE_PIN D6 IOSTANDARD LVCMOS33 } [get_ports { f }];
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set_property -dict { PACKAGE_PIN B5 IOSTANDARD LVCMOS33 } [get_ports { g }];
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set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { dp }];
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set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { an0 }];
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set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { an1 }];
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set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { an2 }];
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set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { an3 }];
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### Button(s)
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set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { reset }];
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@@ -0,0 +1,26 @@
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`timescale 1ns / 1ps
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module tb;
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reg [3:0] char;
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wire [6:0] LED;
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integer i;
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LEDdecoder dut (
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.char(char),
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.LED (LED)
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);
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initial begin
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$dumpfile("wave.vcd");
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$dumpvars(0, tb);
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for (i = 0; i < 16; i = i + 1) begin
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char = i;
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#10;
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$display("char=%h LED{a..g}=%b", char, LED);
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end
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$finish;
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end
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endmodule
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@@ -0,0 +1,60 @@
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`timescale 1ns / 1ps
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module tb_driver;
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reg clk = 0;
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reg reset = 1;
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wire an3, an2, an1, an0;
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wire a, b, c, d, e, f, g, dp;
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FourDigitLEDdriver dut (
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.clk(clk),
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.reset(reset),
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.an3(an3),
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.an2(an2),
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.an1(an1),
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.an0(an0),
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.a(a),
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.b(b),
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.c(c),
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.d(d),
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.e(e),
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.f(f),
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.g(g),
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.dp(dp)
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);
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always #5 clk = ~clk; // 100 MHz
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wire [3:0] low = ~{an3, an2, an1, an0};
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always @(low)
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if ((low & (low - 1)) != 0)
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$display("ERROR t=%0t: επικάλυψη ανόδων, an=%b", $time, {an3, an2, an1, an0});
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always @(an3 or an2 or an1 or an0)
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$display(
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"t=%0t state=%b digit=%h an=%b%b%b%b seg(abcdefg)=%b%b%b%b%b%b%b",
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$time,
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dut.state,
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dut.digit,
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an3,
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an2,
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an1,
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an0,
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a,
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b,
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c,
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d,
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e,
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f,
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g
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);
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initial begin
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$dumpfile("wave_driver.vcd");
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$dumpvars(0, tb_driver);
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#100 reset = 0;
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#20000 $finish;
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end
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endmodule
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@@ -0,0 +1,91 @@
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module FourDigitLEDdriver (
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input clk,
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input reset,
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output an3,
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an2,
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an1,
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an0,
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output a,
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b,
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c,
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d,
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e,
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f,
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g,
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dp
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);
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wire clk_fb, clk_slow_raw, clk_slow, locked;
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MMCME2_BASE #(
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.BANDWIDTH ("OPTIMIZED"),
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.CLKIN1_PERIOD (10.0), // 100 MHz
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.DIVCLK_DIVIDE (1),
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.CLKFBOUT_MULT_F (6.0), // VCO = 600 MHz
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.CLKOUT1_DIVIDE (120), // 600/120 = 5 MHz
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.CLKFBOUT_PHASE (0.0),
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.CLKOUT1_PHASE (0.0),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.STARTUP_WAIT ("FALSE")
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) MMCME2_BASE_inst (
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.CLKIN1(clk),
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.CLKFBIN(clk_fb),
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.CLKFBOUT(clk_fb),
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.CLKOUT1(clk_slow_raw),
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.LOCKED(locked),
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.PWRDWN(1'b0),
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.RST(reset)
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);
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BUFG bufg_slow (
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.I(clk_slow_raw),
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.O(clk_slow)
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);
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wire rst_int = reset | ~locked;
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reg [3:0] state;
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always @(posedge clk_slow or posedge rst_int) begin
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if (rst_int) state <= 4'b1111;
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else state <= state - 1; // one step per 200 ns
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end
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reg [3:0] an;
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reg [3:0] digit;
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always @(*) begin
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case (state)
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4'b1110: an = 4'b0111;
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4'b1010: an = 4'b1011;
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4'b0110: an = 4'b1101;
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4'b0010: an = 4'b1110;
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default: an = 4'b1111;
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endcase
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end
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always @(*) begin
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case (state)
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4'b0000, 4'b1111, 4'b1110, 4'b1101: digit = 4'h0;
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4'b1100, 4'b1011, 4'b1010, 4'b1001: digit = 4'h1;
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4'b1000, 4'b0111, 4'b0110, 4'b0101: digit = 4'h2;
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default: digit = 4'h3;
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endcase
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end
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wire [6:0] LED;
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LEDdecoder LEDdecoder_inst (
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.char(digit),
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.LED (LED)
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);
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assign {an3, an2, an1, an0} = an;
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assign a = ~LED[6];
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assign b = ~LED[5];
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assign c = ~LED[4];
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assign d = ~LED[3];
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assign e = ~LED[2];
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assign f = ~LED[1];
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assign g = ~LED[0];
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assign dp = 1'b1;
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endmodule
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@@ -0,0 +1,24 @@
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module LEDdecoder (
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input [3:0] char,
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output [6:0] LED
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);
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assign LED = (char == 4'h0) ? 7'b1111110 : // 0
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(char == 4'h1) ? 7'b0110000 : // 1
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(char == 4'h2) ? 7'b1101101 : // 2
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(char == 4'h3) ? 7'b1111001 : // 3
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(char == 4'h4) ? 7'b0110011 : // 4
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(char == 4'h5) ? 7'b1011011 : // 5
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(char == 4'h6) ? 7'b1011111 : // 6
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(char == 4'h7) ? 7'b1110000 : // 7
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(char == 4'h8) ? 7'b1111111 : // 8
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(char == 4'h9) ? 7'b1111011 : // 9
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(char == 4'hA) ? 7'b1110111 : // A
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(char == 4'hB) ? 7'b0011111 : // B
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(char == 4'hC) ? 7'b1001110 : // C
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(char == 4'hD) ? 7'b0111101 : // D
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(char == 4'hE) ? 7'b1001111 : // E
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(char == 4'hF) ? 7'b1000111 : // F
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7'b0000000;
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endmodule
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