Initial commit
This commit is contained in:
+74
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#########################################################################################
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## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ##
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||||||
|
## Link : https://github.com/iDoka/eda-scripts ##
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||||||
|
## Description: .gitignore ##
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|
## Usage : just rename or add contain to .gitignore ##
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## License : MIT ##
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#########################################################################################
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||||||
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## log files
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||||||
|
*.log
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||||||
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*.jou
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||||||
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*.rpt
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||||||
|
*.vdi
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||||||
|
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||||||
|
## bitstream
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||||||
|
*.bit
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||||||
|
*.bin
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||||||
|
*.mcs
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||||||
|
*.svf
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||||||
|
*.image
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||||||
|
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||||||
|
## netlist
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||||||
|
*.edf
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||||||
|
*.edif
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||||||
|
*.vn
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||||||
|
*.vm
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||||||
|
|
||||||
|
## SDF
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||||||
|
*.sdf
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||||||
|
|
||||||
|
## sim dump
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||||||
|
*.vcd
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||||||
|
*.saif
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||||||
|
*.tcf
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||||||
|
*.wdb
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||||||
|
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||||||
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## others
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||||||
|
unisims
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||||||
|
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||||||
|
## C-files
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||||||
|
*.elf
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||||||
|
*.a
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||||||
|
*.sa
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||||||
|
*.so
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||||||
|
*.lib
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||||||
|
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||||||
|
## dirs
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||||||
|
vivado.cache/
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||||||
|
vivado.hw/
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||||||
|
vivado.ip_user_files/
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||||||
|
vivado.runs/
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|
vivado.sim/
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||||||
|
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||||||
|
###### for Xilinx Vivado|ISE
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||||||
|
.Xil/
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|
.cache/
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||||||
|
fsm_encoding.os
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||||||
|
tab_*/
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||||||
|
webtalk.*
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||||||
|
vivado_pid*.str
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||||||
|
hs_err_pid*
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||||||
|
xelab.*
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||||||
|
xsim.*
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||||||
|
xvlog.*
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||||||
|
*.cache
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||||||
|
*.sim
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||||||
|
*.runs
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||||||
|
*.hw
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||||||
|
*.backup.*
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|
*.debug
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|
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## checkpoint files
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*.dcp
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|
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@@ -0,0 +1 @@
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The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
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## This file is a general .xdc for the Spartan-7 Boolean Board
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### Clock Signal
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set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { clk }];
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create_clock -add -name sys_clk -period 10.00 -waveform {0 5} [get_ports { clk }];
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### 7-Segment Display
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set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { a }];
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set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { b }];
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set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { c }];
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set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { d }];
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set_property -dict { PACKAGE_PIN A7 IOSTANDARD LVCMOS33 } [get_ports { e }];
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set_property -dict { PACKAGE_PIN D6 IOSTANDARD LVCMOS33 } [get_ports { f }];
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set_property -dict { PACKAGE_PIN B5 IOSTANDARD LVCMOS33 } [get_ports { g }];
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set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { dp }];
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set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { an0 }];
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set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { an1 }];
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set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { an2 }];
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set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { an3 }];
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|
### Button(s)
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|
set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { reset }];
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`timescale 1ns / 1ps
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module tb;
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reg [3:0] char;
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wire [6:0] LED;
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integer i;
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|
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|
LEDdecoder dut (
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|
.char(char),
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.LED (LED)
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|
);
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|
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||||||
|
initial begin
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$dumpfile("wave.vcd");
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$dumpvars(0, tb);
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|
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for (i = 0; i < 16; i = i + 1) begin
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char = i;
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#10;
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$display("char=%h LED{a..g}=%b", char, LED);
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end
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$finish;
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|
end
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endmodule
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@@ -0,0 +1,60 @@
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`timescale 1ns / 1ps
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module tb_driver;
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reg clk = 0;
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reg reset = 1;
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wire an3, an2, an1, an0;
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wire a, b, c, d, e, f, g, dp;
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FourDigitLEDdriver dut (
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.clk(clk),
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.reset(reset),
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.an3(an3),
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.an2(an2),
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.an1(an1),
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.an0(an0),
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.a(a),
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.b(b),
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|
.c(c),
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|
.d(d),
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.e(e),
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.f(f),
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.g(g),
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.dp(dp)
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|
);
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always #5 clk = ~clk; // 100 MHz
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|
wire [3:0] low = ~{an3, an2, an1, an0};
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|
always @(low)
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if ((low & (low - 1)) != 0)
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|
$display("ERROR t=%0t: επικάλυψη ανόδων, an=%b", $time, {an3, an2, an1, an0});
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|
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|
always @(an3 or an2 or an1 or an0)
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|
$display(
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|
"t=%0t state=%b digit=%h an=%b%b%b%b seg(abcdefg)=%b%b%b%b%b%b%b",
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|
$time,
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||||||
|
dut.state,
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|
dut.digit,
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||||||
|
an3,
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||||||
|
an2,
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||||||
|
an1,
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|
an0,
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|
a,
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|
b,
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|
c,
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|
d,
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|
e,
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|
f,
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|
g
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|
);
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|
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|
initial begin
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$dumpfile("wave_driver.vcd");
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$dumpvars(0, tb_driver);
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|
#100 reset = 0;
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|
#20000 $finish;
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|
end
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|
endmodule
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module FourDigitLEDdriver (
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input clk,
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input reset,
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output an3,
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|
an2,
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|
an1,
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|
an0,
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|
output a,
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|
b,
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|
c,
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|
d,
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|
e,
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|
f,
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|
g,
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dp
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|
);
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|
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||||||
|
wire clk_fb, clk_slow_raw, clk_slow, locked;
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|
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|
MMCME2_BASE #(
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|
.BANDWIDTH ("OPTIMIZED"),
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|
.CLKIN1_PERIOD (10.0), // 100 MHz
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|
.DIVCLK_DIVIDE (1),
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|
.CLKFBOUT_MULT_F (6.0), // VCO = 600 MHz
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||||||
|
.CLKOUT1_DIVIDE (120), // 600/120 = 5 MHz
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||||||
|
.CLKFBOUT_PHASE (0.0),
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|
.CLKOUT1_PHASE (0.0),
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|
.CLKOUT1_DUTY_CYCLE(0.5),
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|
.STARTUP_WAIT ("FALSE")
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|
) MMCME2_BASE_inst (
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|
.CLKIN1(clk),
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|
.CLKFBIN(clk_fb),
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|
.CLKFBOUT(clk_fb),
|
||||||
|
.CLKOUT1(clk_slow_raw),
|
||||||
|
.LOCKED(locked),
|
||||||
|
.PWRDWN(1'b0),
|
||||||
|
.RST(reset)
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||||||
|
);
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||||||
|
|
||||||
|
BUFG bufg_slow (
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||||||
|
.I(clk_slow_raw),
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|
.O(clk_slow)
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||||||
|
);
|
||||||
|
|
||||||
|
wire rst_int = reset | ~locked;
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||||||
|
|
||||||
|
reg [3:0] state;
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|
always @(posedge clk_slow or posedge rst_int) begin
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||||||
|
if (rst_int) state <= 4'b1111;
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||||||
|
else state <= state - 1; // one step per 200 ns
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|
end
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|
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|
reg [3:0] an;
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||||||
|
reg [3:0] digit;
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||||||
|
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||||||
|
always @(*) begin
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||||||
|
case (state)
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|
4'b1110: an = 4'b0111;
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|
4'b1010: an = 4'b1011;
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||||||
|
4'b0110: an = 4'b1101;
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||||||
|
4'b0010: an = 4'b1110;
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||||||
|
default: an = 4'b1111;
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||||||
|
endcase
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||||||
|
end
|
||||||
|
|
||||||
|
always @(*) begin
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||||||
|
case (state)
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||||||
|
4'b0000, 4'b1111, 4'b1110, 4'b1101: digit = 4'h0;
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||||||
|
4'b1100, 4'b1011, 4'b1010, 4'b1001: digit = 4'h1;
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||||||
|
4'b1000, 4'b0111, 4'b0110, 4'b0101: digit = 4'h2;
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||||||
|
default: digit = 4'h3;
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||||||
|
endcase
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||||||
|
end
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||||||
|
|
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|
wire [6:0] LED;
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|
LEDdecoder LEDdecoder_inst (
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|
.char(digit),
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|
.LED (LED)
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||||||
|
);
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|
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|
assign {an3, an2, an1, an0} = an;
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|
assign a = ~LED[6];
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|
assign b = ~LED[5];
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|
assign c = ~LED[4];
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|
assign d = ~LED[3];
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||||||
|
assign e = ~LED[2];
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||||||
|
assign f = ~LED[1];
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|
assign g = ~LED[0];
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||||||
|
assign dp = 1'b1;
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||||||
|
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|
endmodule
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@@ -0,0 +1,24 @@
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|
module LEDdecoder (
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|
input [3:0] char,
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output [6:0] LED
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|
);
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|
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||||||
|
assign LED = (char == 4'h0) ? 7'b1111110 : // 0
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(char == 4'h1) ? 7'b0110000 : // 1
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|
(char == 4'h2) ? 7'b1101101 : // 2
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|
(char == 4'h3) ? 7'b1111001 : // 3
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(char == 4'h4) ? 7'b0110011 : // 4
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|
(char == 4'h5) ? 7'b1011011 : // 5
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|
(char == 4'h6) ? 7'b1011111 : // 6
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|
(char == 4'h7) ? 7'b1110000 : // 7
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|
(char == 4'h8) ? 7'b1111111 : // 8
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|
(char == 4'h9) ? 7'b1111011 : // 9
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|
(char == 4'hA) ? 7'b1110111 : // A
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|
(char == 4'hB) ? 7'b0011111 : // B
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|
(char == 4'hC) ? 7'b1001110 : // C
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||||||
|
(char == 4'hD) ? 7'b0111101 : // D
|
||||||
|
(char == 4'hE) ? 7'b1001111 : // E
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||||||
|
(char == 4'hF) ? 7'b1000111 : // F
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||||||
|
7'b0000000;
|
||||||
|
|
||||||
|
endmodule
|
||||||
+225
@@ -0,0 +1,225 @@
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|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<!-- Product Version: Vivado v2018.3 (64-bit) -->
|
||||||
|
<!-- -->
|
||||||
|
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||||
|
|
||||||
|
<Project Version="7" Minor="39" Path="/home/kwstas/Desktop/lab1/lab1.xpr">
|
||||||
|
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||||
|
<Configuration>
|
||||||
|
<Option Name="Id" Val="f3f8e5d3f7534f3a83f95a3990966639"/>
|
||||||
|
<Option Name="Part" Val="xc7s50csga324-1"/>
|
||||||
|
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||||
|
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||||
|
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||||
|
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||||
|
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||||
|
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||||
|
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||||
|
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||||
|
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||||
|
<Option Name="BoardPart" Val=""/>
|
||||||
|
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||||
|
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="ProjectType" Val="Default"/>
|
||||||
|
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||||
|
<Option Name="IPCachePermission" Val="read"/>
|
||||||
|
<Option Name="IPCachePermission" Val="write"/>
|
||||||
|
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||||
|
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||||
|
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||||
|
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||||
|
<Option Name="EnableBDX" Val="FALSE"/>
|
||||||
|
<Option Name="DSAVendor" Val="xilinx"/>
|
||||||
|
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||||
|
<Option Name="WTXSimLaunchSim" Val="2"/>
|
||||||
|
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTXSimExportSim" Val="0"/>
|
||||||
|
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||||
|
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||||
|
<Option Name="WTIesExportSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsExportSim" Val="0"/>
|
||||||
|
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||||
|
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||||
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||||
|
<Option Name="XSimRadix" Val="hex"/>
|
||||||
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||||
|
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||||
|
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||||
|
<Option Name="SimTypes" Val="rtl"/>
|
||||||
|
<Option Name="SimTypes" Val="bfm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||||
|
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||||
|
</Configuration>
|
||||||
|
<FileSets Version="1" Minor="31">
|
||||||
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||||
|
<Filter Type="Srcs"/>
|
||||||
|
<File Path="$PSRCDIR/sources_1/imports/source/LEDdecoder.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="ImportPath" Val="$PPRDIR/../../Downloads/source/LEDdecoder.v"/>
|
||||||
|
<Attr Name="ImportTime" Val="1793755780"/>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/imports/source/FourDigitLEDdriver.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="ImportPath" Val="$PPRDIR/../../Downloads/source/FourDigitLEDdriver.v"/>
|
||||||
|
<Attr Name="ImportTime" Val="1793755724"/>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="FourDigitLEDdriver"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||||
|
<Filter Type="Constrs"/>
|
||||||
|
<File Path="$PSRCDIR/constrs_1/imports/source/boolean.xdc">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="ImportPath" Val="$PPRDIR/../../Downloads/source/boolean.xdc"/>
|
||||||
|
<Attr Name="ImportTime" Val="1793756153"/>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="ConstrsType" Val="XDC"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||||
|
<File Path="$PSRCDIR/sim_1/imports/source/tb_driver.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="ImportPath" Val="$PPRDIR/../../Downloads/source/tb_driver.v"/>
|
||||||
|
<Attr Name="ImportTime" Val="1793755332"/>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sim_1/imports/source/tb.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="AutoDisabled" Val="1"/>
|
||||||
|
<Attr Name="ImportPath" Val="$PPRDIR/../../Downloads/source/tb.v"/>
|
||||||
|
<Attr Name="ImportTime" Val="1793755324"/>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="tb_driver"/>
|
||||||
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="TransportPathDelay" Val="0"/>
|
||||||
|
<Option Name="TransportIntDelay" Val="0"/>
|
||||||
|
<Option Name="SrcSet" Val="sources_1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||||
|
<Filter Type="Utils"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
</FileSets>
|
||||||
|
<Simulators>
|
||||||
|
<Simulator Name="XSim">
|
||||||
|
<Option Name="Description" Val="Vivado Simulator"/>
|
||||||
|
<Option Name="CompiledLib" Val="0"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ModelSim">
|
||||||
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Questa">
|
||||||
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="IES">
|
||||||
|
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Xcelium">
|
||||||
|
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="VCS">
|
||||||
|
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Riviera">
|
||||||
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
</Simulators>
|
||||||
|
<Runs Version="1" Minor="10">
|
||||||
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7s50csga324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7s50csga324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
</Run>
|
||||||
|
</Runs>
|
||||||
|
<Board/>
|
||||||
|
<DashboardSummary Version="1" Minor="0">
|
||||||
|
<Dashboards>
|
||||||
|
<Dashboard Name="default_dashboard">
|
||||||
|
<Gadgets>
|
||||||
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||||
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||||
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
</Gadgets>
|
||||||
|
</Dashboard>
|
||||||
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||||
|
</Dashboards>
|
||||||
|
</DashboardSummary>
|
||||||
|
<BootPmcSettings Version="1" Minor="0">
|
||||||
|
<Parameters/>
|
||||||
|
</BootPmcSettings>
|
||||||
|
</Project>
|
||||||
Reference in New Issue
Block a user