92 lines
1.8 KiB
Verilog
92 lines
1.8 KiB
Verilog
module FourDigitLEDdriver (
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input clk,
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input reset,
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output an3,
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an2,
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an1,
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an0,
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output a,
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b,
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c,
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d,
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e,
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f,
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g,
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dp
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);
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wire clk_fb_out, clk_fb, clk_slow_raw, clk_slow, locked;
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MMCME2_BASE #(
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.BANDWIDTH ("OPTIMIZED"),
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.CLKIN1_PERIOD (10.0), // 100 MHz
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.DIVCLK_DIVIDE (1),
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.CLKFBOUT_MULT_F(6.0), // VCO = 600 MHz
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.CLKOUT1_DIVIDE (120), // 600/120 = 5 MHz
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.STARTUP_WAIT ("FALSE")
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) MMCME2_BASE_inst (
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.CLKIN1 (clk),
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.CLKFBOUT(clk_fb_out),
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.CLKFBIN (clk_fb),
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.CLKOUT1 (clk_slow_raw),
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.LOCKED (locked),
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.PWRDWN (1'b0),
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.RST (reset)
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);
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BUFG bufg_fb (
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.I(clk_fb_out),
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.O(clk_fb)
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);
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BUFG bufg_slow (
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.I(clk_slow_raw),
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.O(clk_slow)
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);
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wire rst_int = reset | ~locked;
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reg [3:0] state;
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always @(posedge clk_slow or posedge rst_int) begin
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if (rst_int) state <= 4'b1111;
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else state <= state - 1; // one step per 200 ns
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end
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reg [3:0] an;
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always @(*) begin
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case (state)
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4'b1110: an = 4'b0111;
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4'b1010: an = 4'b1011;
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4'b0110: an = 4'b1101;
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4'b0010: an = 4'b1110;
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default: an = 4'b1111;
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endcase
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end
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reg [3:0] digit;
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always @(*) begin
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case (state)
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4'b0000, 4'b1111, 4'b1110, 4'b1101: digit = 4'h0;
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4'b1100, 4'b1011, 4'b1010, 4'b1001: digit = 4'h1;
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4'b1000, 4'b0111, 4'b0110, 4'b0101: digit = 4'h2;
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default: digit = 4'h3;
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endcase
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end
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wire [6:0] LED;
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LEDdecoder LEDdecoder_inst (
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.char(digit),
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.LED (LED)
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);
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assign {an3, an2, an1, an0} = an;
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assign a = ~LED[6];
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assign b = ~LED[5];
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assign c = ~LED[4];
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assign d = ~LED[3];
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assign e = ~LED[2];
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assign f = ~LED[1];
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assign g = ~LED[0];
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assign dp = 1'b1;
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endmodule
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