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refactor & add tbs

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This commit is contained in:
Kostas Drakontidis
2026-11-04 12:50:44 +02:00
parent 59f2c10c51
commit 3863bfbecd
11 changed files with 514 additions and 247 deletions
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lab1/lab1.srcs/sim_1/imports/source/tb.v
-26
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@@ -1,26 +0,0 @@
`timescale 1ns / 1ps
module tb;
reg [3:0] char;
wire [6:0] LED;
integer i;
LEDdecoder dut (
.char(char),
.LED (LED)
);
initial begin
$dumpfile("wave.vcd");
$dumpvars(0, tb);
for (i = 0; i < 16; i = i + 1) begin
char = i;
#10;
$display("char=%h LED{a..g}=%b", char, LED);
end
$finish;
end
endmodule
lab1/lab1.srcs/sim_1/imports/source/tb_driver.v
-60
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@@ -1,60 +0,0 @@
`timescale 1ns / 1ps
module tb_driver;
reg clk = 0;
reg reset = 1;
wire an3, an2, an1, an0;
wire a, b, c, d, e, f, g, dp;
FourDigitLEDdriver dut (
.clk(clk),
.reset(reset),
.an3(an3),
.an2(an2),
.an1(an1),
.an0(an0),
.a(a),
.b(b),
.c(c),
.d(d),
.e(e),
.f(f),
.g(g),
.dp(dp)
);
always #5 clk = ~clk; // 100 MHz
wire [3:0] low = ~{an3, an2, an1, an0};
always @(low)
if ((low & (low - 1)) != 0)
$display("ERROR t=%0t: επικάλυψη ανόδων, an=%b", $time, {an3, an2, an1, an0});
always @(an3 or an2 or an1 or an0)
$display(
"t=%0t state=%b digit=%h an=%b%b%b%b seg(abcdefg)=%b%b%b%b%b%b%b",
$time,
dut.state,
dut.digit,
an3,
an2,
an1,
an0,
a,
b,
c,
d,
e,
f,
g
);
initial begin
$dumpfile("wave_driver.vcd");
$dumpvars(0, tb_driver);
#100 reset = 0;
#20000 $finish;
end
endmodule
lab1/partA/partA.srcs/sim_1/new/tb_LEDdecoder.v
+60
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@@ -0,0 +1,60 @@
`timescale 1ns / 1ps
module tb_LEDdecoder;
reg [3:0] char;
wire [6:0] LED;
reg [6:0] expected[0:15];
integer i, errors;
// LED = {a,b,c,d,e,f,g}, 1 = on
localparam [6:0] A = 7'b1000000, B = 7'b0100000, C = 7'b0010000,
D = 7'b0001000, E = 7'b0000100, F = 7'b0000010,
G = 7'b0000001;
LEDdecoder dut (
.char(char),
.LED (LED)
);
// Segment outputs
wire ca = LED[6], cb = LED[5], cc = LED[4], cd = LED[3], ce = LED[2], cf = LED[1], cg = LED[0];
initial begin
expected[4'h0] = A | B | C | D | E | F;
expected[4'h1] = B | C;
expected[4'h2] = A | B | D | E | G;
expected[4'h3] = A | B | C | D | G;
expected[4'h4] = B | C | F | G;
expected[4'h5] = A | C | D | F | G;
expected[4'h6] = A | C | D | E | F | G;
expected[4'h7] = A | B | C;
expected[4'h8] = A | B | C | D | E | F | G;
expected[4'h9] = A | B | C | D | F | G;
expected[4'hA] = A | B | C | E | F | G;
expected[4'hB] = C | D | E | F | G;
expected[4'hC] = A | D | E | F;
expected[4'hD] = B | C | D | E | G;
expected[4'hE] = A | D | E | F | G;
expected[4'hF] = A | E | F | G;
$dumpfile("wave.vcd");
$dumpvars(0, tb_LEDdecoder);
errors = 0;
for (i = 0; i < 16; i = i + 1) begin
char = i;
#10;
if (LED !== expected[i]) begin
errors = errors + 1;
$display("ERROR char=%h LED=%b expected=%b", char, LED, expected[i]);
end
end
if (errors == 0) $display("PASS: 16 tests passed");
else $display("FAIL: %0d tests failed", errors);
$finish;
end
endmodule
lab1/lab1.srcs/sources_1/imports/source/LEDdecoder.v → lab1/partA/partA.srcs/sources_1/imports/source/LEDdecoder.v
+24 -24
View File
@@ -1,24 +1,24 @@
module LEDdecoder (
input [3:0] char,
output [6:0] LED
);
assign LED = (char == 4'h0) ? 7'b1111110 : // 0
(char == 4'h1) ? 7'b0110000 : // 1
(char == 4'h2) ? 7'b1101101 : // 2
(char == 4'h3) ? 7'b1111001 : // 3
(char == 4'h4) ? 7'b0110011 : // 4
(char == 4'h5) ? 7'b1011011 : // 5
(char == 4'h6) ? 7'b1011111 : // 6
(char == 4'h7) ? 7'b1110000 : // 7
(char == 4'h8) ? 7'b1111111 : // 8
(char == 4'h9) ? 7'b1111011 : // 9
(char == 4'hA) ? 7'b1110111 : // A
(char == 4'hB) ? 7'b0011111 : // B
(char == 4'hC) ? 7'b1001110 : // C
(char == 4'hD) ? 7'b0111101 : // D
(char == 4'hE) ? 7'b1001111 : // E
(char == 4'hF) ? 7'b1000111 : // F
7'b0000000;
endmodule
module LEDdecoder (
input [3:0] char,
output [6:0] LED
);
assign LED = (char == 4'h0) ? 7'b1111110 : // 0
(char == 4'h1) ? 7'b0110000 : // 1
(char == 4'h2) ? 7'b1101101 : // 2
(char == 4'h3) ? 7'b1111001 : // 3
(char == 4'h4) ? 7'b0110011 : // 4
(char == 4'h5) ? 7'b1011011 : // 5
(char == 4'h6) ? 7'b1011111 : // 6
(char == 4'h7) ? 7'b1110000 : // 7
(char == 4'h8) ? 7'b1111111 : // 8
(char == 4'h9) ? 7'b1111011 : // 9
(char == 4'hA) ? 7'b1110111 : // A
(char == 4'hB) ? 7'b0011111 : // B
(char == 4'hC) ? 7'b1001110 : // C
(char == 4'hD) ? 7'b0111101 : // D
(char == 4'hE) ? 7'b1001111 : // E
(char == 4'hF) ? 7'b1000111 : // F
7'b0000000;
endmodule
lab1/partA/partA.xpr
+189
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@@ -0,0 +1,189 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2018.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Option Name="Id" Val="ceb0b53e23e94e6d866dd1fe2ec9f563"/>
<Option Name="Part" Val="xc7s50csga324-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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<Option Name="WTModelSimExportSim" Val="0"/>
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<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/imports/source/LEDdecoder.v">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../lab1.srcs/sources_1/imports/source/LEDdecoder.v"/>
<Attr Name="ImportTime" Val="1793785722"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="LEDdecoder"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<File Path="$PSRCDIR/sim_1/new/tb_LEDdecoder.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="tb_LEDdecoder"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7s50csga324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7s50csga324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
<BootPmcSettings Version="1" Minor="0">
<Parameters/>
</BootPmcSettings>
</Project>
lab1/lab1.ip_user_files/README.txt → lab1/partB/partB.ip_user_files/README.txt
View File
lab1/lab1.srcs/constrs_1/imports/source/boolean.xdc → lab1/partB/partB.srcs/constrs_1/imports/source/boolean.xdc
View File
lab1/partB/partB.srcs/sim_1/new/tb_driver.v
+108
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@@ -0,0 +1,108 @@
`timescale 1ns / 1ps
module tb_driver;
reg clk = 0;
reg reset = 1;
wire an3, an2, an1, an0;
wire a, b, c, d, e, f, g, dp;
FourDigitLEDdriver dut (
.clk(clk),
.reset(reset),
.an3(an3),
.an2(an2),
.an1(an1),
.an0(an0),
.a(a),
.b(b),
.c(c),
.d(d),
.e(e),
.f(f),
.g(g),
.dp(dp)
);
always #5 clk = ~clk; // 100 MHz
wire [3:0] an = {an3, an2, an1, an0}; // active-low
wire [3:0] lit = ~an; // 1 = anode enabled
wire [6:0] seg = {a, b, c, d, e, f, g}; // active-low
integer errors = 0;
integer scans = 0;
// 1) No double anodes lit at the same time
always @(an)
if ((lit & (lit - 4'd1)) != 4'd0) begin
errors = errors + 1;
$display("ERROR t=%0t: overlapping anodes an=%b", $time, an);
end
// 2) No segment change on lit anode
realtime t_seg_change = 0;
always @(seg) begin
t_seg_change = $realtime;
if (lit != 4'd0) begin
errors = errors + 1;
$display("ERROR t=%0t: segment change on lit anode", $time);
end
end
// 3) Margin: stable data >= 200 ns before anode off
reg [3:0] prev_lit = 4'd0;
always @(lit) begin
if (prev_lit == 4'd0 && lit != 4'd0 && ($realtime - t_seg_change) < 200.0) begin
errors = errors + 1;
$display("ERROR t=%0t: not enough margin", $time);
end
prev_lit = lit;
end
// 4) Correct digit for each anode (0123, left to right)
task check_seg(input [6:0] expected);
begin
#100;
if (seg !== expected) begin
errors = errors + 1;
$display("ERROR t=%0t: an=%b seg=%b expected=%b", $time, an, seg, expected);
end
end
endtask
always @(an) begin
case (an)
4'b0111: check_seg(7'b0000001); // AN3: 0
4'b1011: check_seg(7'b1001111); // AN2: 1
4'b1101: check_seg(7'b0010010); // AN1: 2
4'b1110: check_seg(7'b0000110); // AN0: 3
default: ;
endcase
end
// 5) Scan period = 16 x 200 ns = 3200 ns
realtime t_an3_fall = 0;
always @(negedge an3) begin
scans = scans + 1;
if (t_an3_fall != 0 &&
(($realtime - t_an3_fall) < 3199.0 || ($realtime - t_an3_fall) > 3201.0)) begin
errors = errors + 1;
$display("ERROR t=%0t: scan period %0f ns", $time, $realtime - t_an3_fall);
end
t_an3_fall = $realtime;
end
initial begin
#100 reset = 0;
#100000; // 100 us (includes MMCM lock)
if (scans < 10) begin
errors = errors + 1;
$display("ERROR: %0d scans (MMCM not locked)", scans);
end
if (errors == 0) $display("PASS: %0d scans no errors", scans);
else $display("FAIL: %0d errors", errors);
$finish;
end
endmodule
lab1/partB/partB.srcs/sources_1/imports/source/LEDdecoder.v
+24
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@@ -0,0 +1,24 @@
module LEDdecoder (
input [3:0] char,
output [6:0] LED
);
assign LED = (char == 4'h0) ? 7'b1111110 : // 0
(char == 4'h1) ? 7'b0110000 : // 1
(char == 4'h2) ? 7'b1101101 : // 2
(char == 4'h3) ? 7'b1111001 : // 3
(char == 4'h4) ? 7'b0110011 : // 4
(char == 4'h5) ? 7'b1011011 : // 5
(char == 4'h6) ? 7'b1011111 : // 6
(char == 4'h7) ? 7'b1110000 : // 7
(char == 4'h8) ? 7'b1111111 : // 8
(char == 4'h9) ? 7'b1111011 : // 9
(char == 4'hA) ? 7'b1110111 : // A
(char == 4'hB) ? 7'b0011111 : // B
(char == 4'hC) ? 7'b1001110 : // C
(char == 4'hD) ? 7'b0111101 : // D
(char == 4'hE) ? 7'b1001111 : // E
(char == 4'hF) ? 7'b1000111 : // F
7'b0000000;
endmodule
lab1/lab1.srcs/sources_1/imports/source/FourDigitLEDdriver.v → lab1/partB/partB.srcs/sources_1/new/FourDigitLEDdriver.v
+91 -91
View File
@@ -1,91 +1,91 @@
module FourDigitLEDdriver (
input clk,
input reset,
output an3,
an2,
an1,
an0,
output a,
b,
c,
d,
e,
f,
g,
dp
);
wire clk_fb, clk_slow_raw, clk_slow, locked;
MMCME2_BASE #(
.BANDWIDTH ("OPTIMIZED"),
.CLKIN1_PERIOD (10.0), // 100 MHz
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (6.0), // VCO = 600 MHz
.CLKOUT1_DIVIDE (120), // 600/120 = 5 MHz
.CLKFBOUT_PHASE (0.0),
.CLKOUT1_PHASE (0.0),
.CLKOUT1_DUTY_CYCLE(0.5),
.STARTUP_WAIT ("FALSE")
) MMCME2_BASE_inst (
.CLKIN1(clk),
.CLKFBIN(clk_fb),
.CLKFBOUT(clk_fb),
.CLKOUT1(clk_slow_raw),
.LOCKED(locked),
.PWRDWN(1'b0),
.RST(reset)
);
BUFG bufg_slow (
.I(clk_slow_raw),
.O(clk_slow)
);
wire rst_int = reset | ~locked;
reg [3:0] state;
always @(posedge clk_slow or posedge rst_int) begin
if (rst_int) state <= 4'b1111;
else state <= state - 1; // one step per 200 ns
end
reg [3:0] an;
reg [3:0] digit;
always @(*) begin
case (state)
4'b1110: an = 4'b0111;
4'b1010: an = 4'b1011;
4'b0110: an = 4'b1101;
4'b0010: an = 4'b1110;
default: an = 4'b1111;
endcase
end
always @(*) begin
case (state)
4'b0000, 4'b1111, 4'b1110, 4'b1101: digit = 4'h0;
4'b1100, 4'b1011, 4'b1010, 4'b1001: digit = 4'h1;
4'b1000, 4'b0111, 4'b0110, 4'b0101: digit = 4'h2;
default: digit = 4'h3;
endcase
end
wire [6:0] LED;
LEDdecoder LEDdecoder_inst (
.char(digit),
.LED (LED)
);
assign {an3, an2, an1, an0} = an;
assign a = ~LED[6];
assign b = ~LED[5];
assign c = ~LED[4];
assign d = ~LED[3];
assign e = ~LED[2];
assign f = ~LED[1];
assign g = ~LED[0];
assign dp = 1'b1;
endmodule
module FourDigitLEDdriver (
input clk,
input reset,
output an3,
an2,
an1,
an0,
output a,
b,
c,
d,
e,
f,
g,
dp
);
wire clk_fb_out, clk_fb, clk_slow_raw, clk_slow, locked;
MMCME2_BASE #(
.BANDWIDTH ("OPTIMIZED"),
.CLKIN1_PERIOD (10.0), // 100 MHz
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F(6.0), // VCO = 600 MHz
.CLKOUT1_DIVIDE (120), // 600/120 = 5 MHz
.STARTUP_WAIT ("FALSE")
) MMCME2_BASE_inst (
.CLKIN1 (clk),
.CLKFBOUT(clk_fb_out),
.CLKFBIN (clk_fb),
.CLKOUT1 (clk_slow_raw),
.LOCKED (locked),
.PWRDWN (1'b0),
.RST (reset)
);
BUFG bufg_fb (
.I(clk_fb_out),
.O(clk_fb)
);
BUFG bufg_slow (
.I(clk_slow_raw),
.O(clk_slow)
);
wire rst_int = reset | ~locked;
reg [3:0] state;
always @(posedge clk_slow or posedge rst_int) begin
if (rst_int) state <= 4'b1111;
else state <= state - 1; // one step per 200 ns
end
reg [3:0] an;
always @(*) begin
case (state)
4'b1110: an = 4'b0111;
4'b1010: an = 4'b1011;
4'b0110: an = 4'b1101;
4'b0010: an = 4'b1110;
default: an = 4'b1111;
endcase
end
reg [3:0] digit;
always @(*) begin
case (state)
4'b0000, 4'b1111, 4'b1110, 4'b1101: digit = 4'h0;
4'b1100, 4'b1011, 4'b1010, 4'b1001: digit = 4'h1;
4'b1000, 4'b0111, 4'b0110, 4'b0101: digit = 4'h2;
default: digit = 4'h3;
endcase
end
wire [6:0] LED;
LEDdecoder LEDdecoder_inst (
.char(digit),
.LED (LED)
);
assign {an3, an2, an1, an0} = an;
assign a = ~LED[6];
assign b = ~LED[5];
assign c = ~LED[4];
assign d = ~LED[3];
assign e = ~LED[2];
assign f = ~LED[1];
assign g = ~LED[0];
assign dp = 1'b1;
endmodule
lab1/lab1.xpr → lab1/partB/partB.xpr
+18 -46
View File
@@ -3,10 +3,10 @@
<!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="39" Path="/home/kwstas/Desktop/lab1/lab1.xpr">
<Project Version="7" Minor="39" Path="C:/Users/MSI/Desktop/dsl/lab1/partB/partB.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="f3f8e5d3f7534f3a83f95a3990966639"/>
<Option Name="Id" Val="ff6d2925ee294a56b08229702e5b4f36"/>
<Option Name="Part" Val="xc7s50csga324-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@@ -31,7 +31,7 @@
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="2"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -50,10 +50,6 @@
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
</Configuration>
<FileSets Version="1" Minor="31">
@@ -61,17 +57,15 @@
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/imports/source/LEDdecoder.v">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../Downloads/source/LEDdecoder.v"/>
<Attr Name="ImportTime" Val="1793755780"/>
<Attr Name="ImportPath" Val="$PPRDIR/../partA/partA.srcs/sources_1/imports/source/LEDdecoder.v"/>
<Attr Name="ImportTime" Val="1793785722"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/source/FourDigitLEDdriver.v">
<File Path="$PSRCDIR/sources_1/new/FourDigitLEDdriver.v">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../Downloads/source/FourDigitLEDdriver.v"/>
<Attr Name="ImportTime" Val="1793755724"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -87,8 +81,8 @@
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/imports/source/boolean.xdc">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../Downloads/source/boolean.xdc"/>
<Attr Name="ImportTime" Val="1793756153"/>
<Attr Name="ImportPath" Val="$PPRDIR/../lab1.srcs/constrs_1/imports/source/boolean.xdc"/>
<Attr Name="ImportTime" Val="1793785722"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
@@ -98,20 +92,9 @@
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<File Path="$PSRCDIR/sim_1/imports/source/tb_driver.v">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/tb_driver.v">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../Downloads/source/tb_driver.v"/>
<Attr Name="ImportTime" Val="1793755332"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/imports/source/tb.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="ImportPath" Val="$PPRDIR/../../Downloads/source/tb.v"/>
<Attr Name="ImportTime" Val="1793755324"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -121,6 +104,7 @@
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="tb_driver"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
@@ -144,36 +128,25 @@
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7s50csga324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7s50csga324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7s50csga324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7s50csga324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -184,7 +157,6 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>