61 lines
1.6 KiB
Verilog
61 lines
1.6 KiB
Verilog
`timescale 1ns / 1ps
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module tb_LEDdecoder;
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reg [3:0] char;
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wire [6:0] LED;
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reg [6:0] expected[0:15];
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integer i, errors;
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// LED = {a,b,c,d,e,f,g}, 1 = on
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localparam [6:0] A = 7'b1000000, B = 7'b0100000, C = 7'b0010000,
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D = 7'b0001000, E = 7'b0000100, F = 7'b0000010,
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G = 7'b0000001;
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LEDdecoder dut (
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.char(char),
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.LED (LED)
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);
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// Segment outputs
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wire ca = LED[6], cb = LED[5], cc = LED[4], cd = LED[3], ce = LED[2], cf = LED[1], cg = LED[0];
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initial begin
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expected[4'h0] = A | B | C | D | E | F;
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expected[4'h1] = B | C;
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expected[4'h2] = A | B | D | E | G;
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expected[4'h3] = A | B | C | D | G;
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expected[4'h4] = B | C | F | G;
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expected[4'h5] = A | C | D | F | G;
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expected[4'h6] = A | C | D | E | F | G;
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expected[4'h7] = A | B | C;
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expected[4'h8] = A | B | C | D | E | F | G;
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expected[4'h9] = A | B | C | D | F | G;
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expected[4'hA] = A | B | C | E | F | G;
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expected[4'hB] = C | D | E | F | G;
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expected[4'hC] = A | D | E | F;
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expected[4'hD] = B | C | D | E | G;
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expected[4'hE] = A | D | E | F | G;
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expected[4'hF] = A | E | F | G;
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$dumpfile("wave.vcd");
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$dumpvars(0, tb_LEDdecoder);
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errors = 0;
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for (i = 0; i < 16; i = i + 1) begin
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char = i;
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#10;
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if (LED !== expected[i]) begin
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errors = errors + 1;
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$display("ERROR char=%h LED=%b expected=%b", char, LED, expected[i]);
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end
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end
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if (errors == 0) $display("PASS: 16 tests passed");
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else $display("FAIL: %0d tests failed", errors);
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$finish;
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end
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endmodule
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