refactor & add tbs
This commit is contained in:
Kostas Drakontidis
@@ -0,0 +1,60 @@
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`timescale 1ns / 1ps
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module tb_LEDdecoder;
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reg [3:0] char;
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wire [6:0] LED;
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reg [6:0] expected[0:15];
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integer i, errors;
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// LED = {a,b,c,d,e,f,g}, 1 = on
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localparam [6:0] A = 7'b1000000, B = 7'b0100000, C = 7'b0010000,
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D = 7'b0001000, E = 7'b0000100, F = 7'b0000010,
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G = 7'b0000001;
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LEDdecoder dut (
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.char(char),
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.LED (LED)
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);
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// Segment outputs
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wire ca = LED[6], cb = LED[5], cc = LED[4], cd = LED[3], ce = LED[2], cf = LED[1], cg = LED[0];
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initial begin
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expected[4'h0] = A | B | C | D | E | F;
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expected[4'h1] = B | C;
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expected[4'h2] = A | B | D | E | G;
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expected[4'h3] = A | B | C | D | G;
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expected[4'h4] = B | C | F | G;
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expected[4'h5] = A | C | D | F | G;
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expected[4'h6] = A | C | D | E | F | G;
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expected[4'h7] = A | B | C;
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expected[4'h8] = A | B | C | D | E | F | G;
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expected[4'h9] = A | B | C | D | F | G;
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expected[4'hA] = A | B | C | E | F | G;
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expected[4'hB] = C | D | E | F | G;
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expected[4'hC] = A | D | E | F;
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expected[4'hD] = B | C | D | E | G;
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expected[4'hE] = A | D | E | F | G;
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expected[4'hF] = A | E | F | G;
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$dumpfile("wave.vcd");
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$dumpvars(0, tb_LEDdecoder);
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errors = 0;
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for (i = 0; i < 16; i = i + 1) begin
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char = i;
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#10;
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if (LED !== expected[i]) begin
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errors = errors + 1;
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$display("ERROR char=%h LED=%b expected=%b", char, LED, expected[i]);
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end
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end
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if (errors == 0) $display("PASS: 16 tests passed");
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else $display("FAIL: %0d tests failed", errors);
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$finish;
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end
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endmodule
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@@ -0,0 +1,24 @@
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module LEDdecoder (
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input [3:0] char,
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output [6:0] LED
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);
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assign LED = (char == 4'h0) ? 7'b1111110 : // 0
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(char == 4'h1) ? 7'b0110000 : // 1
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(char == 4'h2) ? 7'b1101101 : // 2
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(char == 4'h3) ? 7'b1111001 : // 3
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(char == 4'h4) ? 7'b0110011 : // 4
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(char == 4'h5) ? 7'b1011011 : // 5
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(char == 4'h6) ? 7'b1011111 : // 6
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(char == 4'h7) ? 7'b1110000 : // 7
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(char == 4'h8) ? 7'b1111111 : // 8
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(char == 4'h9) ? 7'b1111011 : // 9
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(char == 4'hA) ? 7'b1110111 : // A
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(char == 4'hB) ? 7'b0011111 : // B
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(char == 4'hC) ? 7'b1001110 : // C
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(char == 4'hD) ? 7'b0111101 : // D
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(char == 4'hE) ? 7'b1001111 : // E
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(char == 4'hF) ? 7'b1000111 : // F
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7'b0000000;
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endmodule
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@@ -0,0 +1,189 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2018.3 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="39" Path="C:/Users/MSI/Desktop/dsl/lab1/partA/partA.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="ceb0b53e23e94e6d866dd1fe2ec9f563"/>
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<Option Name="Part" Val="xc7s50csga324-1"/>
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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<Option Name="CompiledLibDirXSim" Val=""/>
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<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
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<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
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<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
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<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
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<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
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<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
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<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
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<Option Name="BoardPart" Val=""/>
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<Option Name="ActiveSimSet" Val="sim_1"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
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<Option Name="ProjectType" Val="Default"/>
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<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
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<Option Name="IPCachePermission" Val="read"/>
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<Option Name="IPCachePermission" Val="write"/>
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<Option Name="EnableCoreContainer" Val="FALSE"/>
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<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
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<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="DSAVendor" Val="xilinx"/>
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<Option Name="DSANumComputeUnits" Val="60"/>
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<Option Name="WTXSimLaunchSim" Val="0"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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<Option Name="WTVcsLaunchSim" Val="0"/>
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<Option Name="WTRivieraLaunchSim" Val="0"/>
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<Option Name="WTActivehdlLaunchSim" Val="0"/>
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<Option Name="WTXSimExportSim" Val="0"/>
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<Option Name="WTModelSimExportSim" Val="0"/>
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<Option Name="WTQuestaExportSim" Val="0"/>
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<Option Name="WTIesExportSim" Val="0"/>
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<Option Name="WTVcsExportSim" Val="0"/>
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<Option Name="WTRivieraExportSim" Val="0"/>
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<Option Name="WTActivehdlExportSim" Val="0"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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<Option Name="XSimRadix" Val="hex"/>
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<Option Name="XSimTimeUnit" Val="ns"/>
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<Option Name="XSimArrayDisplayLimit" Val="1024"/>
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<Option Name="XSimTraceLimit" Val="65536"/>
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<Option Name="SimTypes" Val="rtl"/>
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<Option Name="SimTypes" Val="bfm"/>
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<Option Name="SimTypes" Val="tlm"/>
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<Option Name="SimTypes" Val="tlm_dpi"/>
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<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
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</Configuration>
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<FileSets Version="1" Minor="31">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/sources_1/imports/source/LEDdecoder.v">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../lab1.srcs/sources_1/imports/source/LEDdecoder.v"/>
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<Attr Name="ImportTime" Val="1793785722"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="LEDdecoder"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
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<Filter Type="Constrs"/>
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<Config>
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<Option Name="ConstrsType" Val="XDC"/>
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</Config>
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</FileSet>
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<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
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<File Path="$PSRCDIR/sim_1/new/tb_LEDdecoder.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="tb_LEDdecoder"/>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="TransportIntDelay" Val="0"/>
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<Option Name="SrcSet" Val="sources_1"/>
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</Config>
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</FileSet>
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<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
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<Filter Type="Utils"/>
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<Config>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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</FileSets>
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<Simulators>
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<Simulator Name="XSim">
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<Option Name="Description" Val="Vivado Simulator"/>
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<Option Name="CompiledLib" Val="0"/>
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</Simulator>
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<Simulator Name="ModelSim">
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<Option Name="Description" Val="ModelSim Simulator"/>
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</Simulator>
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<Simulator Name="Questa">
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<Option Name="Description" Val="Questa Advanced Simulator"/>
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</Simulator>
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<Simulator Name="Riviera">
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<Option Name="Description" Val="Riviera-PRO Simulator"/>
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</Simulator>
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<Simulator Name="ActiveHDL">
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<Option Name="Description" Val="Active-HDL Simulator"/>
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</Simulator>
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</Simulators>
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<Runs Version="1" Minor="10">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7s50csga324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<Step Id="synth_design"/>
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</Strategy>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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</Run>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7s50csga324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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</Run>
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</Runs>
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<Board/>
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<DashboardSummary Version="1" Minor="0">
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<Dashboards>
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<Dashboard Name="default_dashboard">
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<Gadgets>
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<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
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</Gadget>
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<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
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</Gadget>
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<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
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</Gadget>
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<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
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</Gadget>
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<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
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<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
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<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
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<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
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</Gadget>
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<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
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</Gadget>
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</Gadgets>
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</Dashboard>
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<CurrentDashboard>default_dashboard</CurrentDashboard>
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</Dashboards>
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</DashboardSummary>
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<BootPmcSettings Version="1" Minor="0">
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<Parameters/>
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</BootPmcSettings>
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</Project>
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